“We want no surprises in meeting our power spec. PowerTheater enables us to detect any errant dynamic power in RTL phase, while taking into account power reduction by clock-gating in low power synthesis,” said Patrick Chan, Low Power Architect for Atheros. “Low power offers a critical competitive advantage for embedded wireless solutions.”

To meet their aggressive power targets, the Atheros design team uses a variety of PowerTheater power reduction techniques, including early power analysis at RTL, architectural exploration, multi-Vt, clock and data gating, automated Wattbots and power linters, and voltage islands.

About Atheros Communications, Inc.

Atheros Communications is a leading developer of semiconductor system solutions for wireless and other network communications products. Atheros combines its wireless and networking systems expertise with high-performance radio frequency (RF), mixed signal and digital semiconductor design skills to provide highly integrated chipsets that are manufactured on low-cost, standard complementary metal-oxide semiconductor (CMOS) processes. Atheros technology is used by a broad base of leading customers, including personal computer, networking equipment and consumer device manufacturers. For more information, please visit www.atheros.com or send email to info@atheros.com.

About Sequence Design

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets. For more information: http://www.sequencedesign.com